1. Field of the Invention
The present invention relates to a silicon epitaxial wafer and the production method thereof. Particularly, the present invention relates to a low specific resistance and large diameter silicon epitaxial wafer that has a reduced warpage and the production method thereof.
2. Description of the Related Art
In recent years, power semiconductor devices have been used for power control, etc. As a wafer for a power semiconductor device, a silicon epitaxial wafer obtained by growing a silicon epitaxial layer almost completely free from any crystal defects on a surface of a silicon wafer obtained by slicing a silicon single crystal ingot grown by the Czochralski (CZ) method is mainly used. Generally, a silicon wafer having a low specific resistance doped with a dopant at a high concentration is used as a silicon wafer for a power semiconductor device.
For attaining a further lower power consumption of a power semiconductor device, a silicon wafer having a lower specific resistance has been demanded. In the case of a p type silicon wafer, a silicon wafer having a low specific resistance is produced by doping, for instance, boron (B) as a dopant at a high concentration. In order to improve the productivity of semiconductor devices, silicon wafers with 300 mm diameter are mainly used instead of silicon wafers with 200 mm diameter. Further, a thickness of a silicon epitaxial layer is apt to increase in connection with a high withstand voltage of a power semiconductor device.
However, when growing a silicon epitaxial layer on a surface of a silicon wafer having a low specific resistance, warpage of the silicon epitaxial wafer is caused because a lattice constant of the silicon wafer and that of the silicon epitaxial layer are different. The warpage becomes larger when a diameter of the wafer becomes larger or when a thickness of the silicon epitaxial layer increases. When the warpage increases, it becomes difficult to make a mask and to hold the silicon epitaxial wafer with vacuum chuck in the device production process and if things come to the worst, it becomes impossible to manufacture semiconductor devices. Consequently, it has become a critical problem to reduce a warpage of a silicon epitaxial wafer as much as possible (See Patent Reference 1). Particularly, in a p/p+ silicon epitaxial wafer obtained by growing a silicon epitaxial layer on a surface of a silicon wafer into which boron is doped at a high concentration, a lattice constant difference is large between the silicon wafer (substrate) doped with boron and the epitaxial layer without being doped, consequently, there has been a disadvantage that a warpage amount of the wafer becomes large after the epitaxial growth.
Also it was found that a silicon epitaxial wafer obtained by growing a silicon epitaxial layer on a surface of a silicon single crystal wafer having a crystal orientation of (110) is more liable to be warped than a silicon epitaxial wafer obtained by growing a silicon epitaxial layer on a surface of a silicon single crystal wafer having a crystal orientation of (100).
[Patent Reference 1] Japanese Patent Laid-open Hei 6-112120